The Transistor at 3 Nanometers

A transistor with a 3-nanometer gate length contains roughly 10 silicon atoms across its critical dimension. An atom of silicon is about 0.22 nanometers in diameter. At this scale, the rules that govern classical electronics — rules that assumed electrons behave like tiny billiard balls, going where the electric field directs them and stopping where the structure tells them to stop — begin to break down. Electrons don't stay where you put them. They tunnel through barriers. They behave as waves, not particles. And the manufacturing tolerances required are so extreme that a single misplaced atom can change device behavior.

This is where Moore's Law ends — not with a wall, exactly, but with a series of increasingly difficult problems that require increasingly exotic solutions. Understanding what those problems are, and how the semiconductor industry is responding to them, is one of the best windows available into the frontier of engineering ambition.

What Moore's Law actually says — and why it's slowing

Gordon Moore's 1965 observation was that the number of components on an integrated circuit was doubling approximately every year (later revised to every two years). This held, with remarkable consistency, for about 50 years. A 1970 Intel processor had 2,300 transistors. A 2023 Apple M3 chip has 25 billion. That's a factor of roughly 10 billion in 53 years — one of the steepest technology curves in history.

The mechanism was simple in principle: shrink everything. Smaller transistors switch faster and consume less power per switch. Smaller features mean more transistors per unit area. Denser transistors mean faster, more capable chips in the same package. For decades, every generation of photolithography — the process of printing circuit patterns using light — could print smaller features. Wavelength got shorter, lenses got more precise, and processes got cleaner.

The first sign of fundamental trouble came with Dennard scaling — the observation, from a 1974 paper by Robert Dennard, that shrinking transistor dimensions proportionally reduced power density, keeping performance-per-watt constant even as chips got faster. Dennard scaling broke around 2005 when leakage current (current flowing through transistors even when they're nominally off) stopped shrinking proportionally. Power density began to rise instead of staying constant. The multi-core era began specifically because you could get more useful work from multiple slower, cooler cores than one blazing fast hot one. Clock speeds, which had been doubling roughly every two years, plateaued around 3–4 GHz and have barely moved since.

Quantum tunneling — the enemy you can't eliminate

Classical electronics treats electrons as classical particles: they have a position, they respond to electric fields, they flow where the channel conducts and stop where the gate closes. At 3nm gate lengths, this picture fails. Quantum mechanics says electrons are waves as much as particles. Waves can penetrate barriers — a phenomenon called quantum tunneling. In a transistor, the gate oxide (the insulating layer separating the gate electrode from the channel) is about 1 nanometer thick at advanced nodes — roughly 4–5 atoms. Electrons tunnel through it directly, flowing from gate to channel even when the transistor is nominally off. This gate leakage current is a fundamental physical limit, not an engineering deficiency to be eliminated by better design.

There's a second tunneling problem: source-to-drain tunneling. As the channel length (the distance between source and drain) shrinks below about 5nm, electrons can tunnel directly from source to drain without being properly controlled by the gate. This subthreshold leakage means the transistor never fully switches off — it leaks current continuously, wasting power and creating noise in logic circuits. The threshold voltage at which the transistor switches becomes poorly defined, reducing noise margins. At some gate length — currently estimated around 1–2nm for silicon — tunneling current becomes so large that the transistor concept breaks down entirely.

What comes after shrinking — the architecture response

The semiconductor industry has responded to the end of simple shrinking with architectural innovation. The FinFET transistor (introduced around 2011) replaced the planar transistor by wrapping the channel material as a vertical "fin" — increasing the effective gate contact area without increasing the gate length, improving electrostatic control and reducing leakage. The Gate-All-Around (GAA) nanosheet transistor (entering production at 3nm nodes) goes further: the gate wraps completely around the channel on all four sides, providing maximum electrostatic control in the smallest possible footprint.

3D integration is now the primary path forward. Rather than packing transistors more densely in 2D, chips are being stacked in three dimensions with copper-to-copper bonding between layers at pitches of a few micrometers. TSMC's SoIC and Intel's Foveros technologies allow dies to be stacked with connections as dense as within a single chip. Memory is stacked directly on processors. Different manufacturing nodes are combined in a single package — leading-edge transistors for compute, trailing-edge nodes for analog and power management — assembled into a chiplet architecture that achieves system-level performance impossible on a single monolithic die.